Time of flight system on a chip

ABSTRACT

A CMOS time-of-flight “TOF” system-on-a-chip “SoC” for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators “CFDs” and a Time-to-Digital Converter “TDC”. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation ( 110 ). The TDC digitizes the time difference with reference to an off-chip precise external clock ( 114 ). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus ( 116 ).

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to and claims the benefit of U.S.Provisional Patent Application Ser. No. 60/371,506, filed Apr. 10, 2002entitled “The Time of Flight System on a Chip (TOF chip)”.

STATEMENT OF GOVERNMENTAL INTEREST

This invention was made with U.S. Government support under contract nos.NAGW-4547 and NAGW5-8516 with NASA. The U.S. Government has certainrights in the invention.

BACKGROUND

There is a broad family of science instruments that benefit from precisetime interval measurement. These instruments include particlespectrometers, delay line UV imagers, laser range finding instruments,etc. In addition, for applications in space, size, weight, and reducedpower dissipation are very desirable characteristics for theseinstruments. A key part of these systems is their electronics. Anattractive solution with respect to the electronics is a very largescale integration (VLSI) System on a Chip (SoC) implementation. Such animplementation can dramatically reduce power dissipation, instrumentsize, and instrument weight significantly increasing the effectivenessof precise time measurement instruments.

SUMMARY

The present invention may be characterized as an integrated analog anddigital time-of-flight (TOF) chip. TOF refers to the ability to captureand digitize precise time intervals. A time interval may be defined asthe time between a start and stop electrical signal. The start and stopsignals can be either analog or digital. The measurement of the unknowntime interval is performed with reference to a known constant timeinterval equal to the period of an external clock. Thus, the three basicinputs to the TOF chip are the start signal, stop signal, and externalclock signal. The result of the measurement is an 11 bit digital wordoutput and a valid event trigger output that indicates a valid result onthe 11 bit output bus. There are other inputs and outputs on the TOFchip including a separate standard microprocessor parallel readout bus,a serial bus, as well as control and test pins.

The TOF chip is comprised of two major functional blocks and a varietyof lesser functional blocks. The first major functional block includestwo constant fraction discriminators (CFDs) for measuring analog startand stop signals. The second major functional block includes atime-to-digital converter (TDC). Other blocks include a phase lockedloop (PLL) that provides a control function for the TDC to lock to theexternal clock. The function of the PLL is very important because itperforms power supply, temperature and radiation compensation tasks.Valid event digital control logic is a function that rejects anomalousevent situations such as double starts, double stops, and the like.Another function includes three event accumulators for counting thetotal number of starts, stops, and valid events. There is a logarithmiccompression function for the output and an averaging function forreducing single shot time jitter.

The complete CFD-TDC functionality is used when the start and stopsignals are analog. TDC only functionality is used when the start andstop signals are digital. The TDC includes a core of 2048 very largescale integration (VLSI) elements. An electric pulse of duration equalto a start-stop time difference T is transmitted through the VLSI core.Core elements truncate the pulse by a certain fixed time (delta T) equalto a digitization step of the TDC commonly known as the leastsignificant bit (LSB). As the pulse propagates through the VLSI core,its duration ultimately diminishes to zero and it disappears. Thedecoding of the position (N) within the core when this takes place istranslated into a measure of the pulse length T where T=N*LSB. The LSBis easily defined by the external clock via the PLL and is in the rangeof −25 ps to 2.5 ns. The maximum time interval measured directly by theTDC is T_(max)=2048*LSB. Longer time intervals are measured by countingclock periods. The combination of fine measurement via the 2048 VLSIcore elements and coarse measurement via clock periods provides a verylarge time interval measurement equal to 32 bits or, 2³²*LSB, that has aresolution as fine as LSB. Thus, Tmax is approximately 0.1 seconds foran LSB of 25 ps and approximately 10 seconds for an LSB of 2.5 ns.

The TOF chip of the present invention includes all of the analog anddigital signal processing necessary for time interval acquisition anddigitization in a single monolithic chip. It is a plug-and-play analog(and/or digital) input digital output device that uses very little powerand provides tremendous resolution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of the time-of-flight (TOF) chip.

FIG. 2 illustrates a block diagram of a constant fraction discriminator(CFD).

FIG. 3 illustrates a block diagram of a time-to-digital converter (TDC).

FIG. 4 illustrates a transistor level diagram of a DLL cell.

FIG. 5 illustrates a block diagram of an energetic particle sensor (EPS)system utilizing the TOF chip of the present invention.

FIG. 6 illustrates the time of flight interval versus energy for fourgroups of ion mass categories.

DETAILED DESCRIPTION

A high level block diagram of a time of flight (TOF) chip according tothe present invention is illustrated in FIG. 1. The TOF chip includestwo constant fraction discriminator (CFD) channels 102, onetime-to-digital conversion (TDC) core 104, valid event logic circuitry106, and event accumulators. The CFDs 102 interface to start-stop MCPanodes 110 via off-chip single transistor amplifiers 112. The TDC core104 digitizes the start-stop time difference using 11-bits, withreference to an off-chip precise clock. An integrated phase locked loop114 (PLL) provides a time reference to the external clock andcompensates for power supply, temperature, and other environmentalvariations.

The valid event logic 106 rejects invalid events such as double starts,stops not associated with a start in a predefined window, single eventupset (SEU) caused errors, and others. An adder/subtractor 116optionally corrects for offsets. Four counters measure the total numberof start, stop, valid event pulses and total number of events (valid ornot) that are processed. For each valid event, a TOF result is provideddirectly onto a bus after a certain processing deadtime. The TOF resultis an 11-bit linear word or an 8-bit quasi-log compressed word.

A block diagram of a CFD 102 channel is illustrated in FIG. 2. Each CFD102 utilizes two comparators 202 a, 202 b, an analog delay line 204, anda voltage divider 206 to form the constant fraction operation. Thebottom comparator 202 a is termed the arming comparator or leading edgediscriminator and it fires when an input pulse crosses a thresholdvalue. The top comparator 202 b is termed the zero crossing comparatorand it fires when the difference of its two inputs switches polarity.The delay line 204 is external to the chip. There is also an optionalon-chip analog delay line with controllable delay in the range of 0.5 nsto 2 ns. Typical delay values are in the range 1 ns to 2 ns for inputpulses with peaking times 3 ns to 6 ns. The comparator baseline isinternally adjusted to 0.5 v_(dd). The comparators 202 a, 202 b areself-compensated to remove offsets with the help of feedback loops. Thegain of the loops is quite large so that the offsets are compensated toless than 0.2 mv. The bandwidth of the two feedback circuits, which isalso controllable off-chip, is selected low compared to the bandwidth ofthe forward chain for overall stability.

A positive input pulse is applied to the arming comparator input Arm+. Adelayed version of the pulse is applied to zero crossing comparatorinput Zcin−, while an attenuated version is applied to input Zcin+. Thearming comparator 202 a fires and sets the flip-flop when the inputamplitude crosses a user-defined threshold. The zero crossing comparator202 b fires at a constant fraction of the input pulse at a timetheoretically independent of the amplitude. An AND combination 208 ofthe two comparators 202 a, 202 b produces a CFD output that, in terms oftiming properties such as time walk and time jitter, is defined by thezero crossing comparator 202 b. Both the arming and CFD outputs areavailable with both polarities.

For precise time pick-off, it may be necessary to operate at as high aspeed as possible so a cascade comparator topology is used. It ispossible to optimize the gain-bandwidth product by selecting the numberof stages and the gain-bandwidth of the individual stages such that theoverall low frequency gain is equal to:A _(V) =Av ₁ · . . . Av ₂ · . . . Av _(i) · . . . Av _(n)  (1)where Av_(i) is the gain of the i^(th) stage. Each stage is comprised ofan operational trans-conductance amplifier (OTA) 210. The transferfunction of an OTA 210 is described by an integrator with a singledominant pole. Assuming equal bandwidth for all stages the frequencydependence of the total gain can be expressed as: $\begin{matrix}{{A_{V}\left( {j\quad\omega} \right)} \cong {\left( {A\quad v_{i}} \right)^{n}\left( \frac{1}{{j\quad\omega\quad\tau} + 1} \right)^{n}}} \\{where} \\{\frac{1}{\tau} \approx {{gm}/{Co}}} \\{and} \\{{Av}_{i} \approx {{gm}/{go}}}\end{matrix}$in which gm, go, and Co are the trans-conductance, the outputconductance, and the parasitic output capacitance for each OTA 210.Solving for ω_(−3dB) yields: $\begin{matrix}{\omega_{{- 3}\quad{dB}} = {\frac{1}{\tau}\sqrt{2^{\frac{1}{n}} - 1}}} & (2)\end{matrix}$

Although the gain increases with the number of stages, overall bandwidthdecreases. Therefore, an optimum number of stages can be selected tomaximize the bandwidth for a given total gain. In this example, the gainof each stage is selected at approximately 3.5 the nominal CFD currentof approximately 1.8 mA and the single stage pole is gm/Co≈2×10⁹rad/sec.

With n=8 for the zero crossing comparator 202 b the overall gain is 87dB and the negative 3 dB bandwidth is 30% of the single stage. With n=5for the arming comparator 202 a the overall gain is 54 dB and thenegative 3 dB bandwidth is 38% of the single stage.

The TDC design is generic to cover a broad range of scientificapplications utilizing different modes of operation. Some generalrequirements of the TDC 104 include: a capability to process both randomand triggered events; a low dead time to process event rates up to 1M/s; stability for temperature, power supply, and environmental effectssuch as radiation (TVE); built-in logic to rapidly reject non-validevents such as double starts, stops with no starts, etc; good integralnon-linearity; and low power dissipation.

The principle of operation of the TDC chip is described in FIGS. 3 and4. Referring to FIG. 3, the start-stop time difference is defined by therising edges of two positive going signals entering a time differencegenerating logic (TDGL) block 302. The TDGL logic 302 additionallyfilters many non-valid events. A valid negative going pulse withduration equal to the start-stop time difference then enters a core of2048 TDC cells 304. Each cell truncates the traveling pulse by a certainfixed time amount Δt, equal to the least significant bit (LSB) of theTDC system. If the start-stop time difference is less thanT_(max=)2048×LSB, the traveling pulse will disappear at a certain celllocation inside the core. Decoding of that cell location yields adigital reading of the event. Decoding is achieved via RS flip-flopscontained in every cell. If the flip-flop of one cell is set and theflip-flop of the next cell is not, the position is decoded using athermometer logic circuit. If start-stop is greater than T_(max), thesystem simply overflows and clears automatically to accept anotherevent.

The basic element of the core, a TDC cell, is illustrated in FIG. 4. TheTDC cell 400 is comprised of a current starving inverter 402 followed bya standard inverter 404. The V_(control) voltage generated by a chargepump circuit 306, controls the rise time of a pulse t_(r1), at theoutput of the current starving inverter 402.

The falling time t_(f1) is defined by a pull down transistor. Thus, theoutput of the first stage is asymmetrical and electronically controlled.The second stage is a standard inverter 404 with properly sizedpull-down and pull-up for symmetrical operation. The cumulative effectof the TDC cell to a negative pulse with duration T is a negative outputpulse with reduced duration. The reduced duration is controllable and isexpressed as delta−T.

The delay introduced to a falling edge traveling through a TDC cell is:t _(f) =t _(r1) +t _(f2)The delay introduced to a rising edge is:t _(r) =t _(f1) +t _(r2)It is possible to design the cell so that approximately:t _(f1) ≅t _(f2) ≅t _(r2)Thus, the total width of the pulse after a TDC cell is reduced by:Δt=t _(f) −t _(r) ≅t _(r1) −t _(r2)We define the time truncation as:delta−T=Δtwhich is the LSB of the TDC system where:LSB≅t _(r1) −t _(r2)  (3)

The processing time required to digitize a start-stop time difference Tthat results in a code N is:T _(N) =Nt _(r) +Twhere t_(r) has been defined as the delay introduced by a single cell toa traveling rising edge. We define the dead time (Tdt) of the TDC as thetime it takes to digitize the maximum time (T_(max)) that results in themaximum code.T_(N) _(max) =N _(max) t _(r) +T _(max)  (4)

The TDC chip is designed to operate in full-core (11-bits) where all2048 cells are used, half-core (10-bits) where only 1024 cells are used,and quarter-core (9-bits) where only 512 cells are used. In each case,the LSB is the same and is defined by the clock. However, the maximummeasurable time and the dead time scale accordingly.

Thus:T _(max 2048)=2048·LSBT _(max 1024) =T _(max 2048)/2T _(max 512) =T _(max 2048)/4Tdt ₂₀₄₈=2048·t _(r) +T _(max 2048)Tdt ₁₀₂₄ =Tdt ₂₀₄₈/2,Tdt ₅₁₂ =Tdt ₂₀₄₈/4.The smaller the dead time, the higher the event rate could be processed.

The LSB as expressed in equation (3) above is a strong function oftemperature, power supply and radiation induced MOS parameter shifts,unless a special control operation is applied to keep it stable.Stability is achieved by implementing a special PLL known as a delaylocked loop (DLL). Parts of the DLL include a time reference generatinglogic (TRGL) block 308 and the charge pump 306. The TRGL 308 applies atrain of negative going pulses with pulse width T_(clk) equal to theperiod of the clock. The charge pump 306 adjusts the V_(control) errorvoltage, so that these pulses disappear on average at the end of the DLLdelay line. The error voltage, V_(control) is low pass filtered andapplied to all 2048 elements of the main TDC core.

The TDC is designed to have two calibration modes of DLL. The first isan open loop DLL, with 2048-elements to make the event measurements anda separate closed loop DLL having 512 elements locked to a referenceclock for the calibration. The second calibration mode is a closed loopDLL, having 2048 elements for both event measurements and thecalibration. Open loop calibration mode is mostly used in random eventcases such as space particles and UV. Closed loop calibration mode isused in triggered event cases such as laser range finding. Closed loopcalibration mode can also be used for random events when it isacceptable to lose a certain number of events during calibration(typically 1% due to slow calibration).

In open loop calibration mode, a pulse of width equal to the period ofthe reference clock is applied every 2048 (or 128) clock periods intothe 512 element calibration DLL. The sum of the 512 element delay isforced to be equal to the clock period, T_(clk). The controlled voltagegenerated by the charge pump is applied to both the 512-elementcalibration DLL and the 2048-element open loop DLL as illustrated inFIG. 3. The LSB in open loop calibration mode becomes: $\begin{matrix}{{LSB}_{{mode}\text{-}a} \cong \frac{Tclk}{512}} & (5)\end{matrix}$and the maximum measurable time becomes:T max_(mod e-a) =T ₂₀₄₈≅4·Tclk.

In closed loop calibration mode, a pulse of width equal to the period ofthe reference clock is applied into the same 2048 element DLL in a timesharing mode with the event measurement. Time sharing is defined by auser supplied calibration trigger. Typically a trigger frequency of 1KHz is enough to compensate for environmental (TVE) effects. Whilecalibrating, the system rejects incoming start-stop events, implying aloss of a small number of events when operating in random mode. The sumof the 2048 element delay is forced to be equal to the clock period,T_(cdk). The control voltage generated by the charge pump is thenapplied to the entire 2048 element closed loop DLL. The LSB in closedloop calibration mode becomes:$\begin{matrix}{{LSB}_{{mode}\text{-}b} \cong \frac{Tclk}{2048}} & (6)\end{matrix}$and the maximum measurable time becomes:T max _(mod e-b) =T ₂₀₄₈ =Tclk.

In the 0.8 u CMOS technology used to fabricate some TOF chips, thecumulative delay of a two-inverter element is approximately 0.6 ns. In atypical case of a 10 MHz-reference clock the following results areexpected for open calibration mode, an LSB_(mod e-a)≈200 ps where themaximum measurable times and dead times are approximately 400 nsmeasurable time and approximately 1200 ns+400 ns dead time for fullcore, approximately 200 ns measurable time and approximately 600 ns+200ns d time for the half core, and approximately 100 ns measurable timeand approximately 300 ns+100 ns d time for the quarter core.

For closed loop calibration mode and a 10 MHz reference clock, theLSB_(mod e-b)≈50 ps where the maximum measurable time is approximately100 ns and dead time is approximately 1200 ns+100 ns.

Another aspect of the DLL is matching between cells in the core and theresulting integral non-linearity (INL) error. However, if INLdistribution is fixed and does not vary with TVE, it can be easilyremoved by post-calibration.

An analysis was performed to derive general matching properties anddesign principles. Mismatches among the TDC cells will result in timeerrors. Process parameters such as transistor trans-conductanceparameter, β=Ko*W/L threshold voltage, V_(t), and gate or diffusioncapacitances, C, are not identical inside the whole chip area. Timetruncation, or the LSB as defined in equation (3) of the single TDC cellof FIG. 4, can be expressed as: $\begin{matrix}{{LSB} \cong {{\left( \frac{C_{i}}{{\beta_{p}\left( {{Vgs} - {Vt}} \right)}^{2}} \right) \times V_{IHi}} - {\left( \frac{C_{o}}{{\beta_{p}\left( {{Vdd} - {Vt}} \right)}^{2}} \right) \times V_{IHe}}}} & (7)\end{matrix}$where C_(i) is the overall internal node capacitance, C_(o) is theoverall output capacitance, β_(p) is the transconductance parameter ofthe pFETs, V_(t) is the threshold voltage of the PFETs,V_(gs)=V_(control) is the gate source voltage that controls the delay ofthe current starved pFET, V_(dd) is the power supply; V_(IHi) is thegate-source voltage at which the internal nFET pulls-down, and V_(IHe)is the gate-source voltage at which the external nFET pulls-down. BothV_(IHi) and V_(IHe) are proportional to the threshold voltage V_(tn) ofthe nFETs. The parenthetic terms of equation (7) approximate the inverseof the rise-time slew rates of the starved and the internal pFETsrespectively.

Assuming independence between all parameters in above expression, thenormalized variance δ₁ ²=δ²(ΔLSB/LSB) of the LSB can be expressed as:$\begin{matrix}{{\sigma^{2}\left( \frac{\Delta\quad{LSB}}{LSB} \right)} = {\sigma_{Ci}^{2} + \sigma_{Co}^{2} + {2\quad\sigma_{\beta_{p}}^{2}} + {2\quad\sigma_{{Vt}_{n}}^{2}} + {{4\left\lbrack {\frac{V_{t}^{2}}{\left( {V_{gs} - V_{t}} \right)^{2}} + \frac{V_{t}^{2}}{\left( {V_{dd} - V_{t}} \right)^{2}}} \right\rbrack}\quad\sigma_{Vt}^{2}}}} & (8)\end{matrix}$where δ_(X) ²=δ²(ΔX/X). Each variance operator δ² in the aboveexpression is inversely proportional to the transistor gate area, δ²approximately 1/WL. In addition matching is improved with a large valueof V_(gs)−V_(t) for all operating conditions. It also helps to use themaximum power supply possible. For the present discussion, much largerthan minimum device areas are described and the cell was optimized tooperate in the 50 ps to 500 ps range with V_(gs) close to V_(dd) at thehigh end time resolution.

It is interesting to investigate how device matching propagates in theDLL chain. The variance of the open (non-controlled) delay line after mdelay elements is simply the sum of the variances of m elements:σ² _(m) =mσ ² ₁  (9)However, the variance of a closed delay line at the N_(th) element willbe different, because of the constraint that the sum of the individualdelays $\sum\limits_{k = 1}^{N}T_{k}$is forced to be constant. The variance at the m element of a DLL of Ntotal elements is described by: $\begin{matrix}{\sigma_{m}^{2} = {\sigma_{1}^{2}\left\lbrack \frac{m \cdot \left( {N - m} \right)}{N} \right\rbrack}} & (10)\end{matrix}$The maximum time variance occurs in the middle of the delay line atm=N/2 with a value: $\begin{matrix}{\sigma_{N/2}^{2} = {\frac{N}{4}\sigma_{1}^{2}}} & (11)\end{matrix}$Thus, the variance of the maximum time deviation of a closed DLL line is¼ the value of the open loop delay line.

In open loop mode of operation, the measurement DLL is open and has 2048elements. The variance at the end will be:σ² _(2048-open)=2048·σ₁ ².

In closed loop mode of operation, the DLL is closed and has 2048elements. The variance at the end will be:σ² _(2048-closed)=512·σ₁ ²and the variance in open loop mode is 4-times worse of that in closedloop mode.

It is possible to fix the increased variance of open loop mode on a chipby chip basis if one measures the maximum processing time of aparticular chip, T max_(mod e-a=T) ₂₀₄₈ _(—) _(measured) in the fullcore selection. This measured value will generally have an offsetbecause it is an open DLL where:T ₂₀₄₈ _(—) _(measured)=4·T _(clk) +T _(offset)  (12)However, T₂₀₄₈ _(—) _(measured) has a fixed value independent of the TVEvariation and a new LSB can be defined as: $\begin{matrix}{{LSB}_{{mode}\text{-}a\text{-}{measured}} \cong \frac{T_{2048{\_ measured}}}{2048}} & (13)\end{matrix}$

With this measured LSB value the open loop DLL behaves like a closedloop DLL in that the total delay is fixed. The INL will again haveminimum values at the beginning and at the end of the DLL and themaximum variance around the expected value based on the measured LSBwill be in the middle and still equal to:N/4σ² ₁=512·σ₁ ².This is achieved because of the measurement of the offset error.

The last consideration pertaining to the TDC is timing jitter error. Inall modes of operation timing jitter is a monotonically increasingfunction of the start-stop time difference because of the additiveeffect of each DLL element. Special care is taken to minimize jittersuch as crosstalk from clock lines with many guard-rings in the layoutetc. The time jitter contribution of the TDC is much less than theoverall time error introduced by the front-end (CFD jitter plus timewalk).

One common measurement in space is the detection of energetic particles.One application specific use for the TOF chip of the present inventionis within a compact Energetic Particle Sensor (EPS) system. The TOF chipreduces EPS system mass to less than 0.5 Kg and power dissipation toless than 0.5 w. These are major improvements over the current state ofthe art.

A top-level schematic that describes the principle of operation of suchan EPS is shown in FIG. 5. For each radiation event the instrument usescombined time-of-flight and energy measurements to discriminate ionspecies.

Energetic particles randomly enter a detector head 502, from an 180°opening through a collimator 504. Particles penetrate a thin foil 506 inthe front and hit an assembly of (six in this case) Solid StateDetectors (SSDs) 508 in the back. Secondary electrons produced in thefront and back foils are electro-statically focused on correspondingstart and stop MCP anodes.

Processing of the start-stop time difference yields the speed of aparticle, and processing of the total charge released in an SSD yieldsparticle energy. Particle mass is determined by combining the TOF andenergy measurements. In addition, a particular SSD address providesangular information.

The goal of the EPS is to discriminate ions in four common masscategories as measured in space (H, He, O, Fe) as well as eight energybands (10 KeV/neucleon to 2 MeV/neucleon). FIG. 6 illustrates the timeof flight interval versus energy for four groups of ion mass categories.In order to discriminate these four mass categories a time resolution ofapproximately 0.5 ns and an energy resolution of approximately 5 KevFWHM are required depending on particular telescope geometries. Adesirable event-processing rate is on the order of 0.1 to 0.2 M/s.Furthermore, it is highly desirable to improve the time and energyresolution in order to discriminate for isotopic mass species and pushthe lowest energy threshold to less than 1 Kev. To achieve thesetargets, the time and energy resolutions should be improved to less than100 ps and less than 0.4 kev FWHM respectively. Additionally the eventthroughput are increased to greater than 1 M/s due to lower energythresholds and the low power nature of the particle distributions.

In the following claims, any means-plus-function clauses are intended tocover the structures described herein as performing the recited functionand not only structural equivalents but also equivalent structures.Therefore, it is to be understood that the foregoing is illustrative ofthe present invention and is not to be construed as limited to thespecific embodiments disclosed, and that modifications to the disclosedembodiments, as well as other embodiments, are intended to be includedwithin the scope of the appended claims. The invention is defined by thefollowing claims, with equivalents of the claims to be included therein.

1. A time-of-flight (TOF) system integrated onto a single chip formeasuring precise time intervals, said system comprising: a firstconstant fraction discriminator for receiving an analog start signalinput and providing a digital output representative of the start signal;a second constant fraction discriminator for receiving an analog stopsignal input and providing a digital output representative of the stopsignal; a logic circuit coupled with the first and second constantfraction discriminators for determining a Δt time interval between thestart and stop signals; and a time-to-digital converter (TDC) receivingas input the Δt time interval between the start and stop signals, saidtime-to-digital converter for digitizing the Δt time interval withreference to an off-chip precise reference clock.
 2. The system of claim1 further comprising valid event logic coupled with the time-to-digitalconverter, the valid event logic for rejecting invalid events.
 3. Thesystem of claim 1 further comprising a phase locked loop coupled withthe time-to-digital converter, the phase locked loop for providing atime reference to the off-chip reference clock and to compensate fortemperature and power supply variations.
 4. The system of claim 1further comprising adder logic coupled with the time-to-digitalconverter, the adder logic for correcting for timing offset.
 5. Thesystem of claim 1 wherein the output of the time-of-flight chip is an11-bit linear word.
 6. The system of claim 1 wherein the output of thetime-of-flight chip is an 8-bit compressed word.
 7. The system of claim1 wherein original digital start and stop signals can be directly inputto the time-to-digital converter bypassing the constant fractiondiscriminators.
 8. The system of claim 1 wherein each constant fractiondiscriminator comprises: an arming comparator having built-in hysterisisfor avoiding multi-firing around a threshold), said arming comparatorfor receiving a positive input pulse wherein the arming comparator fireswhen the positive input pulse crosses a threshold; a zero crossingcomparator for receiving a delayed version of the positive input pulseand an attenuated version of the positive input pulse wherein the zerocrossing comparator fires at a constant fraction of the positive inputpulse; and a logical AND gate coupled with a one-shot for receiving theoutput of the arming comparator and the zero crossing comparator, theAND gate and one-shot providing a digital output for the constantfraction discriminator.
 9. The system of claim 8 wherein each constantfraction discriminator further comprises an on-chip analog delay line.10. The system of claim 1 wherein the time-to-digital convertercomprises: a time difference generating logic component for determininga start-stop time difference defined by the rising edges of two positivegoing signals; a time reference generating logic component for applyinga train of negative going pulses from the reference clock to acalibration delay locked loop DLL; a core of time-to-digital convertercells for receiving a valid negative going pulse of duration equal tothe start-stop time difference wherein each cell truncates the validnegative going pulse by a fixed time; and a position decoding componentfor determining the cell location where the valid negative going pulsedisappeared.
 11. The system of claim 10 wherein each time-to-digitalconverter cell is comprised of: a current starving inverter; and astandard inverter coupled with the current starving inverter, such thata negative pulse of duration T entering a time-to-digital converter cellyields a negative output pulse with a controllable reduced duration.